M13S2561616A_1 Datasheet, PDF (33/49 Pages) Elite Semiconductor Memory Technology Inc. – 4M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
M13S2561616A
Operation Temperature Condition -40~85°C
tCH tCL
tCK
0
1
2
3
4
5
6
7
8
9
10
CLK
CLK
CKE
HIGH
tHP
Note1
CS
RAS
tIS
tIH
CAS
BA0,BA1
BAa
A10/AP
ADDR
(A0~An)
BAa
WE
DQS
DQ
DM
BAb
Cb
tDQSCK
tRPRE
tLZ
tDQSCK
tRPST
Hi-Z
tDQSQ
Da0 Da1
tQH
Da2
tAC
Da3
tHZ
Hi-Z
tDQSS
tWPRE
tDQSL
t
W
P
R
E
t
S
D
Q
S
H
tDS tDH tDS tDH
Db0 Db1 Db2
tWPST
Db3
Hi-Z
Hi-Z
COMMAND
READ
WRITE
Note 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Dec. 2007
Revision : 1.1
33/49