M12L64322A2U Datasheet, PDF (8/46 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks

ESMT
M12L64322A (2U)
SIMPLIFIED TRUTH TABLE
Register
Refresh
COMMAND
Mode Register set
Auto Refresh
Self
Refresh
Entry
Exit
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A9~A0
H
X LL L L X
OP CODE
H
H
LL L H X
X
L
LH H H X
L
H
X
HX X X X
Note
1,2
3
3
3
3
Bank Active & Row Addr.
H
Read &
Auto Precharge Disable
H
Column Address Auto Precharge Enable
Write &
Auto Precharge Disable
H
Column Address Auto Precharge Enable
Burst Stop
H
Bank Selection
Precharge
H
All Banks
Clock Suspend or
Active Power Down
Entry
H
X LL H H X
V
X LH L H X
V
X LH L L X
V
X LH H L X
V
X LL H L X
X
HX X X
L
X
LV V V
Row Address
L Column 4
Address
H _(A0~A7) 4,5
L Column 4
Address
H _(A0~A7) 4,5
X
6
L
X
H
X
Exit
L
H XX X X X
HX X X
Entry
H
L
X
Precharge Power Down Mode
LH H H
X
HX X X
Exit
L
H
X
LV V V
DQM
No Operating Command
H
X
V
X
7
HX X X
H
X
X
X
LH H H
Note:
(V = Valid, X = Don’t Care. H = Logic High, L = Logic Low)
1.OP Code: Operating Code
A0~A10 & BA0~BA1: Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks precharge state.
4.BA0~BA1 : Bank select addresses.
If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected.
If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected
If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected.
5.During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2010
Revision: 1.0
8/46