M12L64322A2U Datasheet, PDF (20/46 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks

ESMT
M12L64322A (2U)
(b) CL =3 ,B L= 4
CLK
i)CMD
DQM
DQ
ii)CMD
DQM
DQ
iii)CMD
DQM
DQ
iv)CMD
DQM
DQ
v)CMD
DQM
DQ
RD WR
D0 D1 D2 _D3
RD
WR
D0 D1 ^{D2 D3}
RD
WR
D0 D1 D2 _D3
RD
WR
Hi-Z
D0 D1 D2 D3
RD
WR
Hi-Z
Q0
D0 D1 D2 _D3
*Note1
*Note: 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
1)Normal Write (BL=4)
CLK
CMD
WR
DQM
*Note3
PRE
*Note2
DQ
D0 D1 D2 D3
*Note:
tRDL(min) M a s k e d b y D Q M
1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of four banks operation.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2010
Revision: 1.0
20/46