M12L64322A2U Datasheet, PDF (34/46 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks

ESMT
M12L64322A (2U)
Page Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
RBb CAa
CBb RCc
RDd CCc
CDd
*Note2
BA1
BA0
A10/AP
RAa
RBb
RCc
RDd
DQ
WE
DQM
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 CDd2
tCDL
tRDL
*Note1
Row Active
( A - Bank )
Write
(A -Ba nk )
Row Active
( B-B ank )
Write
(B -Ba nk )
Row Active
( D- Ba nk )
Write
(D -B an k)
Row Active
( C- Ba nk )
Write
(C -B an k)
Pr echarge
(All Banks)
: Don't care
*Note: 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2010
Revision: 1.0
34/46