M12L64322A2U Datasheet, PDF (37/46 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks

ESMT
M12L64322A (2U)
Clock Suspension & DQM Operation Cycle @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15
16
17 18
19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
Cb
Cc
BA1
BA0
A10/AP
DQ
WE
Ra
tRCD
*Note2
Qa0 Qa1
Qa2
Qa3
tSHZ
DQM
Row Active Read
Clock
Supension
Read
Qb0 Qb1
tSHZ
Dc0
Dc2
*Note1
Read DQM
Write
DQM
Write
Clock
Suspension
Write
DQM
:Don't Care
*Note: 1. DQM is needed to prevent bus contention.
2. tRCD should be met.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2010
Revision: 1.0
37/46