M12L64322A2U Datasheet, PDF (38/46 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks

ESMT
M12L64322A (2U)
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
0
CLOCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 17
18 19
CKE
HIGH
CS
RAS
CAS
ADDR
RAa
BA1
CAa
CAb
BA0
A10/AP
CL=2
DQ
CL=3
RAa
*Note1
*Note1
*Note2
1
QAa0 QAa1 QAa2 QAa3 QAa4
2
QAa0 QAa1 QAa2 QAa3 QAa4
1
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
2
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Burst Stop
Read
(A-Bank)
Precharge
(A-Bank)
:Don't Care
*Note:
1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycles”.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2010
Revision: 1.0
38/46