M12L64322A2U Datasheet, PDF (21/46 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks

ESMT
6. Precharge
1)Normal Write (BL=4)
CLK
WR
DQ
D0 D1 D2 D3
tRDL
*Note1
PRE
M12L64322A (2U)
2)Normal Read (BL=4)
CLK
CMD
RD
DQ(CL2)
PRE CL=2
1*Note2
Q0 Q1 Q2 Q3
CMD
DQ(CL3)
PRE CL=3
2*Note2
Q0 Q1 Q2 Q3
.
7. Auto Precharge
1)Normal Write (BL=4)
2)Normal Read (BL=4)
CLK
CMD
WR
CLK
CMD
RD
DQ
D0 D1 D2 D3
DQ(CL2)
tRDL
*Note3
Auto Precharge starts
DQ(CL3)
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
*Note3
Auto Precharge starts
*Note:
1. tRDL: Last data in to row precharge delay.
2. Number of valid output data after row precharge: 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2010
Revision: 1.0
21/46