M12L64322A2U Datasheet, PDF (6/46 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 32 Bit x 4 Banks

ESMT
M12L64322A (2U)
AC OPERATING TEST CONDITIONS (V_DD = 3.3V ± 0.3V ，T_A = 0 to 70 °C )
Parameter
Value
Unit
Input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall-time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
Output
870 _Ω
3.3V
1200 _Ω
VOH (DC) =2.4V , IOH = -2 mA
30pF
VOL (DC) =0.4V , IOL = 2 mA
Output
Z0 =50 _Ω
Vtt = 1.4V
50 _Ω
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
tRRD(min)
RAS to CAS delay
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time @ Operating
tRC(min)
Last data in to col. address delay tCDL(min)
Last data in to row precharge
tRDL(min)
Last data in to burst stop
tBDL(min)
Col. address to col. address delay tCCD(min)
Number of valid
Output data
CAS latency = 3
CAS latency = 2
Version
-5
-6
-7
10
12
14
15
18
20
15
18
20
40
42
42
100
55
60
63
1
2
1
1
2
1
Unit
ns
ns
ns
ns
us
ns
CLK
CLK
CLK
CLK
ea
Note
1
1
1
1
1
2
2
2
3
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Elite Semiconductor Memory Technology Inc.
Publication Date: Apr. 2010
Revision: 1.0
6/46