M13S5121632A Datasheet, PDF (6/47 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
AC Operating Test Conditions
Parameter
Input reference voltage for clock (V_REF)
Input signal maximum peak swing
Input signal minimum slew rate
Input levels (V_IH/V_IL)
Input timing measurement reference level
Output timing reference level
AC Timing Parameter & Specifications
(V_DD = 2.5V~2.7V, V_DDQ= 2.5V~2.7V, T_A =0 °C ~ 70 °C )
Parameter
Symbol
Clock Period
CL2
CL2.5
CL3
Access time from CLK/ CLK
CLK high-level width
CLK low-level width
Data strobe edge to clock edge
Clock to first rising edge of DQS delay
Data-in and DM setup time (to DQS)
Data-in and DM hold time (to DQS)
DQ and DM input pulse width (for each
input)
Input setup time
Input hold time
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK rising-setup time
DQS falling edge from CLK rising-hold time
Data strobe edge to output data edge
Data-out high-impedance window from
CLK/ CLK
Data-out low-impedance window from
CLK/ CLK
t_CK
t_AC
t_CH
t_CL
t_DQSCK
t_DQSS
t_DS
t_DH
t_DIPW
t_IS
t_IH
t_DQSH
t_DQSL
t_DSS
t_DSH
t_DQSQ
t_HZ
t_LZ
Value
0.5*V_DDQ
1.5
1.0
V_REF+0.31/V_REF-0.31
V_REF
V_TT
-5
min
max
7.5
13
6.0
13
5.0
10
-0.7
+0.7
0.45
0.55
0.45
0.55
-0.6
+0.6
0.75
1.25
0.5
-
0.5
-
1.75
-
0.9
-
0.9
-
0.35
-
0.35
-
0.2
-
0.2
-
-
0.40
-0.7
+0.7
-0.7
+0.7
M13S5121632A
Unit
V
V
V/ns
V
V
V
Unit Note
ns
ns
t_CK
t_CK
ns
t_CK
ns
ns
ns
ns
5
ns
5
t_CK
t_CK
t_CK
t_CK
ns
ns
1
ns
1
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0
6/47