M13S5121632A Datasheet, PDF (4/47 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S5121632A
Absolute Maximum Rating
Parameter
Voltage on any pin relative to V_SS
Voltage on V_DD supply relative to V_SS
Voltage on V_DDQ supply relative to V_SSQ
Storage temperature
Power dissipation
Short circuit current
Symbol
V_IN, V_OUT
V_DD
V_DDQ
T_STG
P_D
I_OS
Value
-0.5 ~ V_DDQ + 0.5
-0.5 ~ 3.7
-0.5 ~ 3.7
-55 ~ +150
1500
50
Unit
V
V
V
°C
mW
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to V_SS = 0V, T_A = 0 to 70 °C )
Parameter
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage (system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CLK and CLK inputs
Input Differential Voltage, CLK and CLK inputs
Input leakage current
Output leakage current
Output High Current (Normal strength driver)
(V_OUT =V_DDQ-0.373V, min V_REF, min V_TT)
Output Low Current (Normal strength driver)
(V_OUT = 0.373V)
Symbol
V_DD
V_DDQ
V_REF
V_TT
V_IH (DC)
V_IL (DC)
V_IN (DC)
V_ID (DC)
I_I
I_OZ
I_OH
I_OL
Min
2.5
2.5
0.49*V_DDQ
V_REF - 0.04
V_REF + 0.15
-0.3
-0.3
0.36
-2
-5
-16.2
+16.2
Max
2.7
2.7
0.51*V_DDQ
V_REF + 0.04
V_DDQ + 0.3
V_REF - 0.15
V_DDQ + 0.3
V_DDQ + 0.6
2
5
Unit
V
V
V
V
V
V
V
V
μA
μA
mA
mA
Note
1
2
3
Notes 1. V_REF is expected to be equal to 0.5* V_DDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on V_REF may not exceed 2% of the DC value.
2. V_TT is not applied directly to the device. V_TT is system supply for signal termination resistors, is expected to be set equal
to V_REF, and must track variations in the DC level of V_REF .
3. V_ID is the magnitude of the difference between the input level on CLK and the input level on CLK .
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0
4/47