M13S5121632A Datasheet, PDF (1/47 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
DDR SDRAM
Features
M13S5121632A
8M x 16 Bit x 4 Banks
Double Data Rate SDRAM
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data access per clock cycle
z Bi-directional data strobe (DQS)
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 2; 2.5; 3
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z V_DD, V_DDQ = 2.5V ~ 2.7V
z Auto & Self refresh
z 7.8us refresh interval (64ms refresh period, 8K cycle)
z SSTL-2 I/O interface
z 66pin TSOPII package
Ordering information:
PRODUCT ID
M13S5121632A -5TG
MAX FREQ
200MHz
VDD
2.5V
PACKAGE
TSOPII
COMMENTS
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0
1/47