M13S5121632A Datasheet, PDF (3/47 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
Pin Arrangement
x1 6
VDD
1
DQ0
2
VDDQ
3
DQ1
4
DQ2
5
VSS Q
6
DQ3
7
DQ4
8
VDDQ
9
DQ5
10
DQ6
11
VSS Q
12
DQ7
13
NC
14
VDDQ
15
LDQS 16
NC
17
VDD
18
NC
19
LDM 20
WE
21
CAS
22
RAS
23
CS
24
NC
25
BA0
26
BA1
27
A10/AP 28
A0
29
A1
30
A2
31
A3
32
VDD
33
66 PIN TSOP(II)
(400mil x 875mil)
(0.65 mm PIN PITCH)
x 16
66
V SS
65
D Q15
64
V SSQ
63
D Q14
62
D Q13
61
V DDQ
60
D Q12
59
D Q11
58
V SSQ
57
D Q10
56
D Q9
55
V DDQ
54
D Q8
53
NC
52
V SSQ
51
U DQS
50
NC
49
V REF
48
V SS
47
U DM
46
CLK
45
CLK
44
C KE
43
NC
42
A 12
41
A 11
40
A9
39
A8
38
A7
37
A6
36
A5
35
A4
34
V SS
M13S5121632A
Pin Description
Pin Name
Function
A0~A12,
BA0,BA1
Address inputs
- Row address A0~A12
- Column address A0~ A9
A10/AP : AUTO Precharge
BA0, BA1 : Bank selects (4 Banks)
DQ0~DQ15 Data-in/Data-out
RAS
CAS
WE
V_SS
V_DD
LDQS, UDQS
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi-directional Data Strobe. LDQS
corresponds to the data on DQ0~DQ7;
UDQS correspond to the data on
DQ8~DQ15.
Pin Name
Function
LDM, UDM
DM is an input mask signal for write
data. LDM corresponds to the data
on DQ0~DQ7; UDM correspond to
the data on DQ8~DQ15.
CLK, CLK
CKE
CS
V_DDQ
V_SSQ
V_REF
Clock input
Clock enable
Chip select
Supply Voltage for GDQ
Ground for DQ
Reference Voltage for SSTL-2
NC
No connection
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0
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