M13S5121632A Datasheet, PDF (5/47 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
DC Specifications
M13S5121632A
Parameter
Symbol
Test Condition
Operation Current
(One Bank Active)
Operation Current
(One Bank Active)
Precharge Power-down
Standby Current
IDD0 ^tRC ^{= t}RC ^{(min), t}CK ^{= t}CK ^{(min), Active – Precharge}
IDD1
Burst Length = 2, t_RC = t_RC (min), CL= 2.5,
I_OUT = 0mA, Active-Read- Precharge
IDD2P CKE ≤ V_IL(max), t_CK = t_CK (min), All banks idle
Idle Standby Current
Active Power-down
Standby Current
Active Standby Current
Operation Current (Read)
Operation Current (Write)
Auto Refresh Current
Self Refresh Current
Operation Current
(Four Bank Operation)
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7
CKE ≥ V_IH(min), CS ≥ V_IH(min), t_CK = t_CK (min)
All banks ACT, CKE ≤ V_IL(max), t_CK = t_CK (min)
One bank; Active-Precharge, t_RC = t_RAS(max),
t_CK = t_CK (min)
Burst Length = 2, CL= 2.5, t_CK = t_CK (min), I_OUT = 0 mA
Burst Length = 2, CL= 2.5, t_CK = t_CK (min)
t_RC ≥ t_RFC(min)
CKE ≤ 0.2V
Four bank interleaving with BL=4, t_RC = t_RC (min),
burst mode; Read with auto precharge;
Address and control inputs on NOP edge are not
changing. I_OUT = 0 mA
Note 1. Enable on-chip refresh and address counters.
AC Operation Conditions & Timing Specification
Version
-5
180
210
10
55
45
60
460
360
290
6
630
Unit Note
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA 1
mA
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Different Voltage, CLK and CLK inputs
Symbol
V_IH(AC)
V_IL(AC)
V_ID(AC)
Min
V_REF + 0.31
0.7
Max
V_REF - 0.31
V_DDQ+0.6
Unit
V
V
V
Note
1
Input Crossing Point Voltage, CLK and CLK inputs
V_IX(AC) 0.5*V_DDQ-0.2 0.5*V_DDQ+0.2
V
2
Note 1. V_ID is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(V_DD = 2.5V~2.7V, V_DDQ = 2.5V~2.7V, T_A = 25 °C , f = 1MHz)
Parameter
Input capacitance
(A0~A11, BA0~BA1, CKE, CS , RAS , CAS , WE )
Symbol
C_IN1
Min
Max
Unit
2.0
3.5
pF
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
C_IN2
C_OUT
C_IN3
2.0
3.5
pF
4.0
5.0
pF
4.0
5.0
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0
5/47