M13S5121632A Datasheet, PDF (43/47 Pages) Elite Semiconductor Memory Technology Inc. – 8M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S5121632A
Power up & Initialization Sequence
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16
17 18 19
CLK
CLK
CKE
High level is required
CS
RAS
CAS
WE
BA0
BA1,A9,
A 11 ~ A 1 2
A10/AP
A8
A7
A1~A6
ADDRESS KEY
A0
DQ
DQS
High-Z
tRP
tMRD
High-Z
Precharge
EMRS
All Bank DLL Enable
(Power & Clock must be
stable for 2 0 0 u s
before precharge
All Bank)
MRS
DLL Reset
Minimum 200 Cycle
tRP
tRC
tRC
Minimum of 2 Refresh Cycles are required
Precharge
All Bank
1st Auto Refresh
2nd Auto Refresh
Any
Command
Mode Resister Set
: Don't Care
Elite Semiconductor Memory Technology Inc.
Publication Date : Oct. 2008
Revision : 1.0
43/47