M12L16161A Datasheet, PDF (6/27 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

M12L16161A
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol ^-4.3
-5
-5.5
-6
-7
-8 _{Unit Note}
Min Max Min Max Min Max Min Max Min Max Min Max
CLK cycle time ^{CAS Latency =3 tCC}
4.3
5
5.5
6
7
8
1000 1000 1000 1000 1000 1000 ns
1
CAS Latency =2
6
7
7.5
8
8.6
10
CLK to valid
output delay
CAS Latency =3
- 4 - 4.5 - 5 - 5.5 - 6 - 6
tSAC
ns 1
CAS Latency =2
- 5- 5- 6- 6- 6- 7
Output data hold time
tOH 2
2
2.5
2.5
2.5
2.5
ns 2
CLK high pulse width
tCH 1.7
2
2
2
2.5
3
ns 3
CLK low pulse width
tCL 1.7
2
2
2
2.5
3
ns 3
Input setup time
tSS 1.7
2
2
2
2
2.5
ns 3
Input hold time
tSH 1
1
1
1
1
1
ns 3
CLK to output in Low-Z
tSLZ 1
1
1
1
1
1
ns 2
CLK to output ^{CAS Latency =3} _tSHZ ^{- 4 - 4.5 - 5 - 5.5 - 6 - 6} ns
in Hi-Z
CAS latency =2
- 5- 5- 6- 6- 6- 7
*All AC parameters are measured from half to half.
Note: 1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to
the parameter.
Elite Semiconductor Memory Technology Inc.
P.6
Publication Date : Jan. 2000
Revision : 1.3u