M12L16161A Datasheet, PDF (18/27 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

M12L16161A
Read & Write Cycle at Different Bank @ Burst Length = 4
CLOCK
0
1
2
3
4
5
6
7
8
9
10
11 12 13
14 ₁₅
16
17 ¹⁸
19
CKE
HIGH
CS
RAS
CAS
ADDR
BA
A10/AP
CL=2
DQ
CL=3
WE
DQM
RAa
RAa
CAa
RBb
RRBBbb
QAa0 QAa1 QAa2 QAa3
QAa0 QAa1 QAa2 QAa3
CBb RAc
CAc
RAc
*Note1
tCDL
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1
Row Active
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
Precharge
(A-Bank)
Write
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
:Don't Care
*Note: 1.tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
P.18
Publication Date : Jan. 2000
Revision : 1.3u