M12L16161A Datasheet, PDF (27/27 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

PACKAGE DIMENSIONS
50-LEAD TSOP(II) SDRAM(400mil)
M12L16161A
D
50
O1.5
1
8.78
(ZD)
-C-
e
b
SEATING PLANE
A
A2
26
DETAIL A
-H-
E1 E
O 2 (4X)
R1
R2
B
25
0.10 C
A1
-C-
O 3 (4X)
GAGE
O PLANE
-C-
O1
B
DETAIL A
L
L1
WITH PLATING
BASE METAL
b
c1 c
SECTION B-B
b1
Symbol
A
A1
A2
b
b1
c
c1
D
ZD
E
E1
L
L1
R1
ððð^Rð2²³´
Min
-
0.05
0.95
0.30
0.30
0.12
0.10
20.82
11.56
10.03
0.40
0.12
0.12
0
0
10
10
Dimension in mm
Nom
-
0.10
1.00
-
0.35
-
0.127
20.95
0.875 REF
11.76
10.16
0.50
0.80 REF
0.80 BSC
-
-
-
-
15
15
Max
1.20
0.15
1.05
0.45
0.40
0.21
0.16
21.08
11.96
10.29
0.60
-
0.25
8
-
20
20
Min
-
0.002
0.037
0.012
0.012
0.005
0.004
0.820
0.455
0.394
0.016
0.005
0.005
0
0
10
10
Dimension in inch
Nom
-
0.004
0.039
-
0.014
-
0.005
0.825
0.034 REF
0.463
0.400
0.020
0.031 REF
0.031 BSC
-
-
-
-
15
15
Max
0.047
0.006
0.041
0.018
0.016
0.008
0.006
0.830
0.471
0.405
0.024
0.010
8
-
20
20
Elite Semiconductor Memory Technology Inc.
P.27
Publication Date : Jan. 2000
Revision : 1.3u