M12L16161A Datasheet, PDF (1/27 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

M12L16161A
512K x 16Bit x 2Banks Synchronous DRAM
FEATURES
z JEDEC standard 3.3V power supply
z LVTTL compatible with multiplexed address
z Dual banks operation
z MRS cycle with address key programs
GENERAL DESCRIPTION
The M12L16161A is 16,777,216 bits synchro-
nous high data rate Dynamic RAM organized as
2 x 524,288 words by 16 bits, fabricated with
high performance CMOS technology. Synchro-
- CAS Latency (2 & 3 )
nous design allows precise cycle control with the
- Burst Length (1, 2, 4, 8 & full page)
use of system clock I/O transactions are possible
- Burst Type (Sequential & Interleave)
on every clock cycle. Range of operating fre-
z All inputs are sampled at the positive going edge quencies, programmable burst length and pro-
of the system clock
z Burst Read Single-bit Write operation
z DQM for masking
z Auto & self refresh
z 32ms refresh period (2K cycle)
grammable latencies allow the same device to be
useful for a variety of high bandwidth, high
performance memory system applications.
ORDERING INFORMATION
Part NO.
M12L16161A-4.3T
M12L16161A-5T
M12L16161A-5.5T
M12L16161A-6T
M12L16161A-7T
M12L16161A-8T
MAX Freq.
233MHz
200MHz
183MHz
166MHz
143MHz
125MHz
Interface
LVTTL
Package
50
TSOP(II)
PIN CONFIGURATION (TOP VIEW)
VDD
1
DQ0
2
DQ1
3
VSSQ
4
DQ2
5
DQ3
6
VDDQ
7
DQ4
8
DQ5
9
VSSQ
10
DQ6
11
DQ7
12
VDDQ
13
LDQM 14
WE
15
CAS
16
RAS
17
CS
18
BA
19
A10/AP 20
A0
21
A1
22
A2
23
A3
24
VDD
25
50 VSS
49 DQ15
48 DQ14
47 VSSQ
46 DQ13
45 DQ12
44 VDDQ
43 DQ11
42 DQ10
41 VSSQ
40 DQ9
39 DQ8
38 VDDQ
37 N.C/RFU
36 UDQM
35 CLK
34 CKE
33 N.C
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
Elite Semiconductor Memory Technology Inc.
P.1
Publication Date : Jan. 2000
Revision : 1.3u