M12L16161A Datasheet, PDF (23/27 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

M12L16161A
Burst Read Single bit Write Cycle @Burst Length=2
0
1
CLOCK
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
CKE
*Note 1
HIGH
CS
RAS
CAS
ADDR
RAa
BA
A10/A P
RAa
CAa RBb CAb
RBb
*Note 2
RAc
CBc
CAd
RAc
C L =2
DQ
CL =3
DAa0
DAa0
QA b0 QAb1
QAb0 ^QAb1
DBc0
DBc0
QAd0 QA d1
QA d0 QAd1
WE
DQM
Row Active
(A-Bank)
Row Active
(B-Bank)
W ri te
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Row Active
( A -Ba nk )
Read
(A -Ba nk )
Write with
Auto Precharge
(B-Bank)
Pr ec ha rg e
( A -Ba nk )
:Don't Care
*Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.
2.When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge
command will be issued after two clock cycles.
Elite Semiconductor Memory Technology Inc.
P.23
Publication Date : Jan. 2000
Revision : 1.3u