M12L16161A Datasheet, PDF (2/27 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

FUNCTIONAL BLOCK DIAGRAM
M12L16161A
Bank Select
Data Input Register
LWE
LDQM
512K x 16
DQi
CLK
512K x 16
ADD
Column Decoder
LCKE
LRAS LCBR LWE
Latency & Burst Length
Programming Register
LCAS
LWCBR
LDQM
Timing Register
CLK CKE _CS RAS CAS WE L(U)DQM
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System Clock
Input Function
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10/AP Address
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
BA
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
CAS
WE
L(U)DQM
DQ0 ~ 15
VDD/VSS
Row Address Strobe
Column Address Strobe
Write Enable
Data Input / Output Mask
Data Input / Output
Power Supply/Ground
Latches row addresses on the positive going edge of the CLK with RAS
low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Elite Semiconductor Memory Technology Inc.
P.2
Publication Date : Jan. 2000
Revision : 1.3u