M12L16161A Datasheet, PDF (24/27 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

M12L16161A
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
0
CLOCK
CKE
CS
1
2
3
4
tSS
*Note1
*Note3
5
6
7
8
*Note 2
tSS
9 10 11 12 13 14 15 16 17 18 19
tSS
RAS
CAS
ADD R
BA
Ra
Ca
A10/AP
DQ
WE
DQM
Ra
tSHZ
Qa0 Qa1 Qa2
P rec ha rg e
Power-D ow n
En t r y
Row Active
Precharge
Power-Down
Exit
Active
Power-down
Entry
Read
Active
Power-down
Exit
P r ec h a r g e
: Don't care
*Note :1.Both banks should be in idle state prior to entering precharge power down mode.
2.CKE should be set high at least 1CLK+tss prior to Row active command.
3.Can not violate minimum refresh specification. (32ms)
Elite Semiconductor Memory Technology Inc.
P.24
Publication Date : Jan. 2000
Revision : 1.3u