M12L16161A Datasheet, PDF (20/27 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

M12L16161A
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
Ca
BA
Cb
Cc
A10/AP
Ra
DQ
WE
DQM
Qa0 Qa1
Qa 2
Qa3
tSHZ
Qb0 Qb1
tSHZ
Dc0
Dc2
*Note1
Row Active Read
Clock
S u sp en s i o n
Read
Read DQM
Write
DQM
Write
DQM
Write
Clock
S u s p en s i o n
*Note:1.DQM is needed to prevent bus contention.
:Don't Care
Elite Semiconductor Memory Technology Inc.
P.20
Publication Date : Jan. 2000
Revision : 1.3u