GD25Q128C Datasheet, PDF (49/69 Pages) ELM Electronics – 128M-bit Serial Flash

GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
7.31. Individual Block/Sector Lock (36H)/Unlock (39H)/Read (3DH)
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The individual block/sector lock provides an alternative way to protect the memory array from adverse Erase/
Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must be set to 1. If
WPS=0, the write protection will be determined by the combination of CMP, BP (4:0) bits in the Status Register.
The Individual Block/Sector Lock bits are volatile bits. The default values after device power up or after a Reset
are 1, so the entire memory array is being protected.
The individual Block/Sector Lock command (36H) sequence: CS# goes low → SI: Sending individual Block/
Sector Lock command → SI: Sending 24bits individual Block/Sector Lock Address → CS# goes high. The
command sequence is shown in Figure34.
The individual Block/Sector Unlock command (39H) sequence: CS# goes low → SI: Sending individual
Block/Sector Unlock command → SI: Sending 24bits individual Block/Sector Lock Address → CS# goes high.
The command sequence is shown in Figure35.
The Read individual Block/Sector lock command (3DH) sequence: CS# goes low → SI: Sending Read
individual Block/Sector Lock command → SI: Sending 24bits individual Block/Sector Lock Address → SO:
The Block/Sector Lock Bit will out → CS# goes high. If the least significant bit(LSB) is1, the corresponding
block/sector is locked, if the LSB is 0, the corresponding block/sector is unlocked, Erase/Program operation can
be performed. The command sequence is shown in Figure36.
Figure 34. Individual Block/Sector Lock command Sequence Diagram
CS#
SCLK
SI
0123456789
29 30 31
Command
36H
24 Bits Address
23 22
210
MSB
Figure 34a. Individual Block/Sector Lock command Sequence Diagram (QPI)
CS#
SCLK
IO₀
IO₁
IO₂
IO₃
012345 67
Command
36H _{A23-16 A12-8}
20 16 12 8
A7-0
40
21 17 13 9 5 1
22 18 14 10 6 2
23 19 15 11 7 3
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Rev.1.2