GD25Q128C Datasheet, PDF (18/69 Pages) ELM Electronics – 128M-bit Serial Flash

GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
7.1. Write Enable (WREN)(06H)
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The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch
(WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE),
Write Status Register (WRSR) and Erase/Program Security Register command. The Write Enable (WREN)
command sequence: CS# goes low → sending the Write Enable command → CS# goes high.
Figure 3. Write Enable Sequence Diagram
CS#
SCLK
SI
SO
01234567
Command
06H
High-Z
Figure 3a. Write Enable Sequence Diagram (QPI)
CS#
SCLK
IO₀
01
Command
06H
IO₁
IO₂
IO₃
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command
sequence: CS# goes low → Sending the Write Disable command → CS# goes high. The WEL bit is reset by
following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,
Block Erase, Chip Erase, Erase/Program Security Register and Reset commands.
Figure 4. Write Disable Sequence Diagram
CS#
SCLK
SI
SO
01234567
Command
04H
High-Z
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Rev.1.2