GD25Q128C Datasheet, PDF (26/69 Pages) ELM Electronics – 128M-bit Serial Flash

GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
7.11. Quad I/O Fast Read (EBH)
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The Quad I/O Fast Read command is similar to the Dual I/O Fast Read command but with the capability to
input the 3-byte address (A23-0) and a “Continuous Read Mode” byte and 4-dummy clock 4-bit per clock
by IO0, IO1, IO2, IO3, each bit being latched in during the rising edge of SCLK, then the memory contents
are shifted out 4-bit per clock cycle from IO0, IO1, IO2, IO3. The command sequence is shown in followed
Figure13. The first byte addressed can be at any location. The address is automatically incremented to the next
higher address after each byte of data is shifted out. The Quad Enable bit (QE) of Status Register (S9) must
be set to enable for the Quad I/O Fast read command.
Quad I/O Fast Read with “Continuous Read Mode”
The Quad I/O Fast Read command can further reduce command overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the “Continuous Read Mode” bits (M5-4)
=(1, 0), then the next Quad I/O Fast Read command (after CS# is raised and then lowered) does not require the
EBH command code. The command sequence is shown in followed Figure13a. If the “Continuous Read Mode”
bits (M5-4) do not equal to (1, 0), the next command requires the first EBH command code, thus returning
to normal operation. A “Continuous Read Mode” Reset command can be used to reset (M5-4) before issuing
normal command.
Figure 13. Quad I/O Fast Read Sequence Diagram (M5-4 ≠ (1, 0))
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SI(IO0)
SO(IO1)
Command
EBH
40404040
51515151
4040 4
5151 5
WP#(IO2)
62626262
6262 6
HOLD#(IO3)
73737373
A23-16 A15-8 A7-0 M7-0
Dummy
7373 7
Byte1 Byte2
Figure 13a. Quad I/O Fast Read Sequence Diagram (M5-4 = (1, 0))
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SI(IO0)
SO(IO1)
WP#(IO2)
HOLD#(IO3)
40404040
4040 4
51515151
5151 5
62626262
6262 6
73737373
A23-16 A15-8 A7-0 M7-0
Dummy
7373 7
Byte1 Byte2
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Rev.1.2