GD25Q128C Datasheet, PDF (47/69 Pages) ELM Electronics – 128M-bit Serial Flash

GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
7.29. Program Security Registers (42H)
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The Program Security Registers command is similar to the Page Program command. It allows from 1 to 512
bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have been
executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers command. The
Program Security Registers command is entered by driving CS# Low, followed by the command code (42H),
three address bytes and at least one data byte on SI. As soon as CS# is driven high, the self-timed Program
Security Registers cycle (whose duration is tPP) is initiated. While the Program Security Registers cycle is in
progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in
Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked.
Program Security Registers command will be ignored.
Address
A23-A16
A15-A12
A11-A9
A8-A0
Security Register #1
00H
Security Register #2
00H
Security Register #3
00H
0001
0010
0011
000
000
000
Byte Address
Byte Address
Byte Address
Figure 32. Program Security Registers command Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
SI
CS#
SCLK
Command
42H
24-bit address
Data Byte 1
23 22 21
321076543210
MSB
MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte 256
SI
7654321076543210
76543210
MSB
MSB
MSB
69 - 47
Rev.1.2