GD25Q128C Datasheet, PDF (21/69 Pages) ELM Electronics – 128M-bit Serial Flash

GD25Q128CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
7.5. Write Status Register (WRSR) (01H or 31H or 11H)
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The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it
can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable
(WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S20, S19, S17, S16, S15, S10, S1 and S0 of
the Status Register. CS# must be driven high after the eighth of the data byte has been latched in. If not, the
Write Status Register (WRSR) command is not executed. As soon as CS# is driven high, the self-timed Write
Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the
Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,
BP3, BP2, BP1 and BP0) bits, to define the size of the area that is to be treated as read-only. The Write
Status Register (WRSR) command also allows the user to set or reset the Status Register Protect (SRP1 and
SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP1 and SRP0)
bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write
Status Register (WRSR) command is not executed once the Hardware Protected Mode is entered.
Figure 7. Write Status Register Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
Status Register in
SI
01H/31H/11H 7 6 5 4 3 2 1 0
SO
MSB
High-Z
Figure 7a. Write Status Register Sequence Diagram (QPI)
CS#
SCLK
IO₀
IO₁
IO₂
IO₃
0123
Command
01H/31H/11H
40
51
62
73
Status Register in
69 - 21
Rev.1.2