MA28140 Datasheet, PDF (7/72 Pages) Dynex Semiconductor – Packet Telecommand Decoder

MA28140
Priority Mode
In this mode two inputs have priority, according to the
following rule: TC0 > TC1 > TC2 = TC3 = TC4 = TC5. When
neither the TC0 input nor the TC1 input is active, the selection
between the inputs TC2 to TC5 is performed as in the
Standard Mode.
As soon as the TC active signal of TC0 is asserted, this TC
input is selected, and the 5 other channels are inhibited. In
case another input was already selected and receiving data, it
is abandoned. The TC0 input remains selected until one of the
following events:
a1: its TC active signal becomes inactive, or
b1: its bit clock has not been received for a period equal to
the TC clock timeout, or
c1: no Start Sequence has been detected for a period
equal to the TC active timeout, or
d1: a Tail Sequence or a codeblock rejection has occurred.
Upon events (a1) and (d1), the selection logic returns to
the search state. Upon events (b1) and (c1), the TC0 input is
ignored (i.e. considered inactive) until the event (a1) occurs.
When the TC0 input is inactive (including the case of a
timeout as described above), as soon as the TC active signal
of TC1 is asserted, this TC input is selected, and the lower
priority inputs TC2 to TC5 are inhibited. In case any of these
inputs was already selected and receiving data, it is
abandoned. The TCl input remains selected until one of the
following events.
a2: its TC active signal, becomes inactive, or
b2: its bit clock has not been received for a period equal to
the TC clack timeout, or
c2: no Start Sequence has been detected for a period
equal to the TC active timeout, or
d2: a Tail Sequence or a codeblock rejection has occurred,
or
e2: the TCO active signal is asserted.
Upon events (a2) and (d2), the selection logic returns to the
search state. Upon events (b2) and (c2), the selection logic
ignores the TC1 input until event (a2) occurs. Upon event (e2)
the TCl input is inhibited and the TC0 input is selected as
previously described.
The TC clock timeout value between two successive edges
of the TC channel clock is: 3932160 t_CK < TC clock timeout <
4587520 t_CK. With a system clock frequency f_CK of 4 MHz this
equals 0.98s <TC clock timeout < 1.15s.
The TC active timeout value between two successive Start
Sequence patterns being detected is 334233600 t_CK < TC
active timeout < 335399960 t_CK. With a system clock
frequency f_CK of 4MHz this equals 83.5s < TC active timeout <
83.9s.
Codeblock Decoding
Codeblock decoding is performed for each received
codeblock. At the sending end, a systematic block coding
procedure processing 56 bits per Codeblock and generating 7
parity check bits per Codeblock is used. The parity check bits
are then complemented and placed into the codeblocks: P0
(MSB) through P6 are located in the first seven bits (MSBs) of
the last octet of the codeblock. The last bit of the last octet, P7
(LSB), is a filler bit appended to complete the 8-bit Error Control
Field. This Filler Bit should normally be a zero, except for the
Tail Sequence. The code is a (63,56) modified Bose-Chaudhuri-
Hocquenghem (BCH), based on the following polynomial
generator: g(x)=x⁷+x⁶+x²+1. A single error correction & double
error detection mode is provided by using this code.
The following table describes the Decoding Strategy of the
codeblocks:
ERRORS DETECTED
no errors
even number of errors
odd number of errors
with a binary syndrome
value equal to all zeros
odd number of errors
with a binary syndrome
value different from all
zeros
odd number of errors
with a binary syndrome
value different from all
zeros
FILLER BIT
VALUE
ignored
ignored
ignored
0
1
DECISION
codeblock
accepted
codeblock
rejected
codeblock
rejected
codeblock
accepted
correction of
a single error
codeblock
rejected
CLTU Management
CLTU decoding consists of the states and events
summarized in the following table and state diagram:
S1
INACTIVE
E1
E2(c)
E4
S2
SEARCH
E3
E2(b)
S3
DECODE
E2(a)
Figure 4: CLTU Decoder State Diagram
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