MA28140 Datasheet, PDF (61/72 Pages) Dynex Semiconductor – Packet Telecommand Decoder

MA28140
T imin g
De scription
Min
Typ
Tr1
CLK rising to LADR valid
0 ns
Tr2
CLK falling to RWN valid
0 ns
Tr3
CLK rising to CSN asserted
0 ns
Tr4
CLK rising to CSN deasserted
0 ns
Tr5
CLK falling to RWN invalid
0 ns
Tr6
LDAT setup to CSN deasserted
100 ns
Tr7
LDAT hold after CSN deasserted
0 ns
Tr8 (1)
LACK setup to CLK falling
20 ns
Tr9 (1)
LACK hold after CLK falling
20 ns
Tr10
CSN pulse width deasserted
2 Tck
Note (1): Violation will lead to uncertainty about the number of wait states inserted.
Table 21: Memory Read Timings
Max
150 ns
57 ns
67 ns
68 ns
57 ns
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