MA28140 Datasheet, PDF (37/72 Pages) Dynex Semiconductor – Packet Telecommand Decoder

Case 1: RAM is used to store the 8 bits of Recovery LAC counter
BACK-UP POWER
PTD
VDD
VSS
AUTSL
AUEXT
LADR
LDAT 8
RWN
RAMCSN
LACCS
AD
DAT
WE
CS
RAM
MA28140
Case 2: A device different from the RAM is used to store the 8 bits of Recovery LAC counter
PTD
VSS
VSS
AUTSL
AUEXT
LADR
LDAT 8
RWN
RAMCSN
LACCS
RAM
AD
DAT
WE
CS
NON-VOLATILE
DAT
WE
LAC value
CS
Figure 20: Recovery LAC Value Storage
A diagram of two possible implementations is given in
Figure 20.
The RAM mapping is organized in such a way that the PTD
is able to use the following external RAM buffers:
• two buffers working in a flip-flop mode between transfer
and segmentation layer, respectively called Front End
and Back End buffer.
• one buffer used by the CPDU interface
The buffer management is described in section 4.2. The
memory mapping is defined in tables 5 and 6.
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