MA28140 Datasheet, PDF (53/72 Pages) Dynex Semiconductor – Packet Telecommand Decoder

MA28140
Example of an aborted data transfer.
T imin g
De scription
Min
Typ
Max
Tmapst0 (1) (3) MAPSTN low pulse width
1 Tck
Tmapst1
LDAT hold after MAPSTN rising
0.5 Tck
Tmapst2
MAPST rising to MADSR rising
2 Tck
1 Tmapck + 2 Tck
Tmapst3
LDAT setup to MAPSTN falling
0.5 Tck
Tmapst4
MAPSTN rising to MAPDATA valid
2 Tck
1 Tmapck + 2 Tck
Tmaps1
MAPDTR high to MAPCK rising
0.5 Tmapck
1.5 Tmapck + 1 Tck
Tmaps2 (3)
MAPCK falling to MAPDSR falling
1 Tmapck
Tmaps3
MAPDTR setup to MAPCK falling
2 Tck
Tmapck (2)
MAPCK period
2 Tck
[2¹³] Tck
Tmapout
MAPCK falling to MAPDATA valid
-5 ns
10 ns
Tmapdtr
MAPDTR high pulse width
2 Tck
Tmapadt (3)
MAPADT high pulse width
2 Tmapck
Tmaps4 (3)
MAPCK falling to MAPADT rising
1 Tmapck
Tmaps5
MAPDSR falling to MAPDSR rising
56 Tck
Tmaps6 (3)
MAPADT rising to MAPDSR falling
1 Tmapck
Tmaps7 (4)
MAPDSR rising to MAPCK rising
0.5 Tmapck
1.5 Tmapck
Note (1): This timing is specified with no wait state configuration (LACK permanently asserted). The
asserting of this signal is identical with the asserting of the RAMCSN signal in a write cycle.
Note (2): Tmapck period is programmable as defined in section 5.2.
Note (3): These timings are exact with a variance of -10ns to +10ns.
Note (4): This timing is for a data transfer with MAPDTR permanently asserted.
Table 14: Serial MAP Interface Timings
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