MA28140 Datasheet, PDF (42/72 Pages) Dynex Semiconductor – Packet Telecommand Decoder

MA28140
6. STATE AFTER RESET
Asserting the RESETN signal asynchronously forces the local bus interface to avoid bus contention. The master clock should
be started before RESETN deassertion. After 2 master clock cycles, the PTD is in a stable state and all its outputs take their cold
start value. Deasserting the RESETN signal starts the initialisation phase. After this phase, the PTD registers are initialised.
PTD Outputs After the Assertion of RESETN Input
- LADR<10..0>
- LDAT<7..0>
- RWN
- RAMCSN
- ROMCSN
- LACCS
- all other outputs at unknown state
—> 000
—> ZZ
—> 1
—> 1
—> 1
—> 0
PTD Outputs After the Reset Sequence
- LADR<10..0>
- LDAT<7..0>
- RWN
- BGRN
- RAMCSN
- ROMCSN
- LACCS
- MAPSTN
- MAPCK
- MAPDSR
- MAPDATA
- MAPADT
- CPDUSTN
- CPDUEN
- CLCWDA
- TMD
- CLCWDB
- PRDY
- PBUS<15..0>
- AUST
- AUBUF
- AUSBUF
- FARBUF
- SELTC<2..0>
- DECOD
—> 000
—> ZZ
—> 1
—> 1
—> 1
—> 1
—> 0
—> 1
—> 0
—> 0
—> 0
—> 0
—> 1
—> 0
—> 0
—> 0
—> 0
—> 0
—> ZZZZ
—> 0
—> 1
—> 0
—> 0 after Reset, 1 after initialization (FAR write)
—> 111
—> 0
PTD Outputs After the Initialisation Phase
CODING LAYER:
The coding layer is ready to receive a frame after the reset.
TRANSFER LAYER:
The transfer layer initialisation state after reset is the following:
• FARM-1 state
• FARMB counter
• V(R) counter
: lockout
: 11
: 00000000
The cold start value of the CLCW (2 octets) is X000 (where X can be hexadecimal 2, 6, A or E).
The value of the MSB (No RF available) depends on the value of the RFAVN pin. The value of the second MSB (No Bit Lock)
depends on the activation of the Tca signals (see section 4.6).
AUTHENTICATION LAYER:
The cold start initialisation state for the AU layer can be summarized as follows if AUDis = 0 and AUExt = 0:
- Key in use
- Contents of programmable key
- Contents of Principal and Auxiliary LAC Registers
- Contents of the Recovery LAC counter
: fixed key
: undefined
: all ones
: unchanged by the PTD
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