MA28140 Datasheet, PDF (60/72 Pages) Dynex Semiconductor – Packet Telecommand Decoder

MA28140
CPDU Interface
PTD
CPDUDIV
CPDUSTN
CPDUEN
LDAT<7..0>
CPDU
External
Module
T imin g
De scription
Min
Typ
Max
Tc1
LDAT setup to CPDUSTN falling
0.5 Tck
Tc2 (1) (2)
CPDUSTN low pulse width
1 Tck
Tc3
LDAT hold after CPDUSTN rising
0.5 Tck
Tc4
CPDUSTN falling to CPDUEN rising
D/2 - 3 Tck
Tc5 (2)
CPDUEN falling to CPDUSTN falling
D/2 + 1 Tck
Tc6
CPDUEN high pulse width
D + Tck
[2^X]xD + Tck 128D + Tck
D (1)
CPDUDIV = 0
40960 Tck
D (1)
CPDUDIV = 1
8192 Tck
Note (1): This timing is specified with no wait state configuration (LACK permanently asserted). The asserting of
this signal is identical with the asserting of the RAMCSN signal in a write cycle.
Note (2): These timings are exact with a variance of -10ns to +10ns.
Table 20: CPDU Interface Timings
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