DS80C390_05 Datasheet, PDF (51/53 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

DS80C390 Dual CAN High-Speed Microprocessor
MESSAGE BUFFERING/OVERWRITE
If a message center is configured for reception (T/R = 0) and the previous message has not been read (DTUP = 1),
then the disposition of an incoming message to that message center is controlled by the WTOE bit (located in CAN
Arbitration Register 3 of each message center). When WTOE = 0, the incoming message is discarded and the
current message is untouched.
If the WTOE bit is set, the incoming message is received and written over the existing data bytes in that message
center. The receiver overwrite bit (ROW) is also set in the corresponding message center control register, located
in SFR memory.
Message center 15 is unique in that it incorporates a buffer that can receive up to two messages without loss. If a
message is received by message center 15 while it contains an unread message, the new incoming message is
held in an internal buffer. When the CAN processor reads the message-center-15 memory location and then clears
DTUP = INTRQ = EXTRQ = 0, the contents of the internal buffer is automatically loaded into the message-center-
15 MOVX-memory location.
The message-center-15 WTOE bit controls what happens if a third message is received when both the message-
center-15 MOVX-memory location and the buffer contain unread messages. If WTOE = 0, the new message is
discarded, leaving the message-center-15 MOVX-memory location and the buffer untouched. If WTOE = 1, then
the third message writes over the buffered message but leaves the message-center-15 MOVX-memory location
untouched.
ERROR COUNTER INTERRUPT GENERATION
Each CAN module can be independently configured to alert the microprocessor when either 96 or 128 errors have
been detected by the transmit or receive error counters. The error count select bit, ERCS (C0C.1 or C1C.1) selects
whether the limit is 96 (ERCS = 0) or 128 (ERCS = 1) errors. When the error limit is exceeded, the CAN error count
exceeded bit, CECE (C0S.6 or C1S.6), bit is set. If the ERIE, C0IE (or C1IE), and EA SFR bits are configured, an
interrupt is generated. If the ERCS bit is set, the device generates an interrupt when the CECE bit is set or cleared,
if the interrupt is enabled.
BIT TIMING
Bit timing of the CAN transmission can be adjusted per the CAN 2.0B specification. The CAN 0/1 bus timing
register zero (C0BT0 and C1BT0)—located in the control/status/mask register block in MOVX memory—controls
the PHASE_SEG1 and PHASE_SEG2 time segments as well as the baud-rate prescaler (BPR5–BPR0). The CAN
0/1 bus timing register one (C0BT1 and C1BT1) contains the controls for the sampling rate and the number of clock
cycles assigned to the Phase Segment 1 and 2 portions of the nominal bit time. The values of both bus timing
registers are automatically loaded into the CAN processor following each software change of the SWINT bit from a
1 to a 0 by the microcontroller. The bit timing parameters must be set before starting operation of the CAN
processor. These registers can only be modified during a software initialization, (SWINT = 1), when the CAN
processor is NOT in a bus-off mode, and after the removal of a system reset or a CAN reset. To avoid
unpredictable behavior of the CAN processor, the software cannot clear the SWINT bit when TSEG1 and TSEG2
are both cleared to 0.
51 of 53