DS80C390_05 Datasheet, PDF (50/53 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

DS80C390 Dual CAN High-Speed Microprocessor
Table 14. Arbitration/Masking Feature Summary
TEST NAME
ARBITRATION
REGISTERS
MASK REGISTERS
Standard 11-Bit
Arbitration (CAN
2.0A)
Message Center
Arbitration Registers 0–1
(Located in each
Message Center, MOVX
memory)
Standard Global Mask
Registers 0–1
(Located in each CAN
Control/Status/Mask
Register bank, MOVX
memory)
Extended 29-Bit
Arbitration (CAN
2.0B)
Message Center
Arbitration Registers 0–3
(Located in each
Message Center, MOVX
memory)
Extended Global Mask
Registers 0–3
(Located in each CAN
Control/Status/Mask
Register bank, MOVX
memory)
Media Byte
Arbitration
Media Arbitration
Registers 0–3
(Located in each CAN
Control/Status/Mask
Register bank, MOVX
memory)
Media ID Mask Registers
0–1
(Located in each CAN
Control/Status/Mask
Register bank, MOVX
memory)
Message Center
15, Standard
11-Bit Arbitration
(CAN 2.0A)
Message Center 15
Arbitration Registers 0–1
(Located in Message
Center 15, MOVX
memory)
Message Center 15 Mask
Registers 0–1
(Located in each CAN
Control/Status/Mask
Register bank, MOVX
memory)
Message Center
15, Extended
29-Bit Arbitration
(CAN 2.0B)
Message Center 15
Arbitration Registers 0–3
(Located in Message
Center 15, MOVX
memory)
Message Center 15 Mask
Registers 0–3
(Located in each CAN
Control/Status/Mask
Register bank, MOVX
memory)
CONTROL BITS AND CONDITIONS
EX/ST = 0
MEME = 0: Mask register ignored. ID and
arbitration register must match exactly.
MEME = 1: Only bits corresponding to 1 in mask
register are compared in ID and arbitration
registers.
EX/ST = 1
MEME = 0: Mask register ignored. ID and
arbitration register must match exactly.
MEME = 1: Only bits corresponding to 1 in mask
register are compared in ID and arbitration
registers.
MDME = 0: Media byte arbitration disabled.
MDME = 1: Only bits corresponding to 1 in
Media ID mask register are compared between
data bytes 1 and 2 and Media arbitration
registers.
EX/ST = 0
MEME = 0: Mask register ignored. ID and
arbitration register must match exactly.
MEME = 1: Message center 15 mask registers
are ANDed with Global Mask register. Only bits
corresponding to 1 in resulting value are
compared in ID and arbitration registers.
EX/ST = 1
MEME = 0: Mask register ignored. ID and
arbitration register must match exactly.
MEME = 1: Message center 15 mask registers
are ANDed with Global Mask register. Only bits
corresponding to 1 in resulting value are
compared in ID and arbitration registers.
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