DS80C390_05 Datasheet, PDF (35/53 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

DS80C390 Dual CAN High-Speed Microprocessor
INTERNAL MOVX SRAM
The DS80C390 contains 4kB of SRAM that can be configured as user accessible MOVX memory, program
memory, or optional stack memory. The specific configuration and locations are governed by the internal data
memory configuration bits (IDM1, IDM0) in the memory control register (MCON;C6h). Note that when the SA bit
(ACON.2) is set, the first 1kB of the MOVX data memory is reserved for use by the 10-bit expanded stack. Internal
memory accesses will not generate WR, RD, or PSEN strobes.
The DS80C390 can configure its 4kB of internal SRAM as combined program and data memory. This allows the
application software to execute self-modifiable code. The technique loads the 4kB SRAM with bootstrap loader
software, and then modifies the IDM1 and IDM0 bits to map the 4kB starting at memory location 40000h. This
allows the system to run the bootstrap loader without disturbing the 4MB external memory bus, making the device
in-system reprogrammable for flash or NV RAM.
Table 5. Internal MOVX SRAM Configuration
IDM1 IDM0 CMA
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MOVX DATA
00F000h–00FFFFh
00F000h–00FFFFh
000000h–000FFFh
000000h–000FFFh
400000h–400FFFh
400000h–400FFFh
—
—
MEMORY
CAN MESSAGE
00EE00h–00EFFFh
401000h–4011FFh
00EE00h–00EFFFh
401000h–4011FFh
00EE00h–00EFFFh
401000h–4011FFh
00EE00h–00EFFFh
401000h–4011FFh
*10-bit expanded stack is not available in shared program/data memory mode.
SHARED PROGRAM/DATA
—
—
—
—
—
—
400000h–400FFFh*
400000h–400FFFh*
EXTERNAL MEMORY ADDRESSING
The enabling and mapping of the chip-enable signals is done through the Port 4 control register (P4CNT;92h) and
memory control register (MCON; 96h). Table 7 shows which chip-enable and address line signals are active on
Port 4. Following reset, the device will be configured with P4.7–P4.4 as address lines and P4.3–P4.0 configured as
CE3-0, with the first program fetch being performed from 00000h with CE0 active. The following tables illustrate
which memory ranges are controlled by each chip enable as a function of which address lines are enabled.
Table 6. External Memory Addressing Pin Assignments
ADDRESS/DATA
BUS
Multiplexed
CE3–CE0
P4.3–P4.0
PCE3–PCE0
P5.7–P5.4
ADDR 19–16 ADDR 15–8
P4.7–P4.4
P2
Demultiplexed
P4.3–P4.0
P5.7–P5.4
P4.7–P4.4
P2
ADDR 7–0
P0
P1
DATA BUS
P0
P0
Table 7. Extended Address and Chip-Enable Generation
P4CNT.5–3
000
100
101
110
111(default)
PORT 4 PIN FUNCTION
P4.7
P4.6
P4.5
P4.4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A16
I/O
I/O
A17
A16
I/O
A18
A17
A16
A19
A18
A17
A16
P4CNT.2–0
000
100
101
110
111(default)
P4.3
I/O
I/O
I/O
I/O
CE3
PORT 4 PIN FUNCTION
P4.2
P4.1
P4.0
I/O
I/O
I/O
I/O
I/O
CE0
I/O
CE1
CE0
CE2
CE1
CE0
CE2
CE1
CE0
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