DS80C390_05 Datasheet, PDF (5/53 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

DS80C390 Dual CAN High-Speed Microprocessor
MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 12)
PARAMETER
SYMBOL
MOVX ALE Pulse Width
Port 0 MOVX Address, CE0–4,
PCE0–4 Valid to ALE Low
Address Hold After MOVX
Read/Write
RD Pulse Width
WR Pulse Width
RD Low to Valid Data In
Data Hold After Read
Data Float After Read
t_LHLL2
t_AVLL2
t_LLAX2
t_LLAX3
t_RLRH
t_WLWH
t_RLDV
t_RHDX
t_RHDZ
ALE Low to Valid Data In
Port 0 Address, Port 4 CE, Port 5
PCE to Valid Data In
Port 2, 4 Address to Valid Data In
t_LLDV
t_AVDV1
t_AVDV2
ALE Low to RD or WR Low
Port 0 Address, Port 4 CE, Port 5
PCE to RD or WR Low
Port 2, 4 Address to or WR Low
Data Valid to WR Transition
Data Hold After WR High
RD Low to Address Float
RD or WR High to ALE, Port 4 CE
or Port 5 PCE High
t_LLWL
t_AVWL1
t_AVWL2
t_QVWX
t_WHQX
t_RLAZ
t_WHLH
MIN
0.375 t_MCS - 5
0.5 t_MCS - 5
1.5 t_MCS - 10
0.125 t_MCS - 5
0.25t_MCS - 5
1.25 t_MCS - 10
0.25t_MCS-5
0.125 t_MCS - 5
1.25 t_MCS - 5
0.5 t_MCS - 6
C_ST x t_MCS - 10
0.5 t_MCS - 6
C_ST x t_MCS - 10
0
0.125 t_MCS - 5
0.25t_MCS - 5
1.25 t_MCS - 5
0.25 t_MCS - 11
0.5t_MCS - 11
2.5 t_MCS - 11
0.375 t_MCS - 11
0.625t_MCS - 11
2.625 t_MCS - 11
-8
0.25 t_MCS - 8
0.5t_MCS - 10
1.5 t_MCS - 10
-5
0.25 t_MCS - 7
1.25 t_MCS - 7
MAX
0.5 t_MCS - 20
C_ST x t_MCS - 25
0.25 t_MCS - 5
0.5t_MCS - 5
1.5 t_MCS - 5
0.625 t_MCS - 20
(C_ST + 0.25) x t_MCS - 20
(C_ST + 1.25) x t_MCS - 20
0.75 t_MCS - 26
(4C_ST + 0.5) x t_MCS - 30
(4C_ST + 2.5) x t_MCS - 30
0.75 t_MCS - 30
(4C_ST + 0.5) x t_MCS - 30
(4C_ST + 2.5) x t_MCS - 30
0.125 t_MCS + 10
0.25t_MCS + 10
1.25 t_MCS + 10
See Note 12
+10
0.25 t_MCS + 5
1.25 t_MCS +10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STRETCH
VALUES
C_ST (MD2:0)
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST =0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
C_ST = 0
1 ≤ C_ST ≤ 3
4 ≤ C_ST ≤ 7
Note 12:
All parameters apply to both commercial and industrial temperature operation. C_ST is the stretch cycle value determined by the
MD2:0 bits. t_MCS is a time period shown in the t_MCS Time Periods table. All signals characterized with load capacitance of 80pF
except Port 0, ALE, PSEN, RD, and WR with 100pF. Interfacing to memory devices with float times over 25ns can cause bus
contention and an increase in operating current. Specifications assume a 50% duty cycle for the oscillator; port 2 and ALE timing
changes in relation to duty cycle variation. Some AC timing characteristic drawings show the CLK signal, provided to determine the
relative occurrence of events and not the timing of signals relative to the external clock. During the external addressing mode, weak
latches maintain the previously driven value from the processor on Port 0 until Port 0 is overdriven by external memory; and on Port
1, 2 and 4 for one XTAL1 cycle prior to change in output address from Port 1, 2, and 4.
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