DS80C390_05 Datasheet, PDF (30/53 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

DS80C390 Dual CAN High-Speed Microprocessor
Because the device runs the standard 8051 instruction set, in general, software written for existing 80C32-based
systems will work on the DS80C390. The primary exceptions are related to timing-critical issues, since the high-
performance core of the microcontroller executes instructions much faster than the original. Memory interfacing is
performed identically to the standard 80C32. The high-speed nature of the DS80C390 core slightly changes the
interface timing, and designers are advised to consult the timing diagrams in this data sheet for more information.
The DS80C390 provides the same timer/counter resources, full duplex serial port, 256 bytes of scratchpad RAM
and I/O ports as the standard 80C32. Timers default to a 12 clocks-per-machine cycle operation to keep timing
compatible with original 8051 systems, but can be programmed to run at the faster four clocks-per-machine cycle if
desired. New hardware functions are accessed using special function registers that do not overlap with standard
80C32 locations.
This data sheet provides only a summary and overview of the DS80C390. Detailed descriptions are available in the
High-Speed Microcontroller User’s Guide: DS80C390 Supplement. This data sheet assumes a familiarity with the
architecture of the standard 80C32. In addition to the basic features of that device, the DS80C390 incorporates
many new features.
PERFORMANCE OVERVIEW
The DS80C390’s higher performance comes not just from increasing the clock frequency but also from a more
efficient design. This updated core removes the dummy memory cycles that are present in a standard, 12 clocks-
per-machine cycle 8051. In the DS80C390, the same machine cycle takes 4 clocks. Thus the fastest instruction,
one machine cycle, executes three times faster for the same crystal frequency. The majority of instructions on the
DS80C390 see the full 3-to-1 speed improvement, while a few execute between 1.5 and 2.4 times faster.
Regardless of specific performance improvements, all instructions are faster than the original 8051.
Improvement of individual programs depends on the actual mix of instructions used. Speed-sensitive applications
should make the most use of instructions that are three times faster. However, the large number of 3-to-1 improved
op codes makes dramatic speed improvements likely for any arbitrary combination of instructions. These
architecture improvements and the submicron CMOS design produce a peak instruction cycle in 100ns (10 MIPS).
The dual data pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory.
INSTRUCTION SET SUMMARY
All instructions perform exactly the same functions as their 8051 counterparts. Their effect on bits, flags, and other
status functions is identical. However, the timing of instructions is different, both in absolute and relative number of
clocks. The absolute timing of software loops can be calculated using a table in the High-Speed Microcontroller
User’s Guide: DS80C390 Supplement. However, counter/timers default to run at the traditional 12 clocks per
increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed.
Timers optionally can run at the faster four clocks per increment to take advantage of faster processor operation.
The relative time of two DS80C390 instructions might differ from the traditional 8051. For example, in the original
architecture the “MOVX A, @DPTR” instruction and the “MOV direct, direct” instruction required the same amount
of time: two machine cycles or 24 oscillator cycles. In the DS80C390, the MOVX instruction takes as little as two
machine cycles, or eight oscillator cycles, but the “MOV direct, direct” uses three machine cycles, or 12 oscillator
cycles. While both are faster than their original counterparts, they now have different execution times. This is
because the device usually uses one instruction cycle for each instruction byte. Examine the timing of each
instruction for familiarity with the changes. Note that a machine cycle now requires just four clocks, and provides
one ALE pulse per cycle. Many instructions require only one cycle, but some require five. Refer to the High-Speed
Microcontroller User’s Guide: DS80C390 Supplement for details and individual instruction timing.
SPECIAL FUNCTION REGISTERS (SFRs)
Special function registers (SFRs) control most special features of the microcontroller, allowing the device to have
many new features but use the same instruction set as the 8051. When writing software to use a new feature, an
equate statement defines the SFR to an assembler or compiler. This is the only change needed to access the new
function. The DS80C390 duplicates the SFRs contained in the standard 80C52. Table 1 shows the register
addresses and bit locations. Many are standard 80C52 registers. The High-Speed Microcontroller User’s Guide:
DS80C390 Supplement contains a full description of all SFRs.
30 of 53