DS80C390_05 Datasheet, PDF (25/53 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

PIN DESCRIPTION
PIN
LQFP
PLCC
8, 22, 40, 17, 32, 51,
56
68
9, 25, 41, 1, 18, 35,
57
52
46
57
45
56
47
58
26
36
2
11
3
12
23
33
24
34
55
67
54
66
53
65
52
64
51
63
50
62
49
61
48
59
NAME
V_CC
GND
ALE
PSEN
EA
MUX
RST
RSTOL
XTAL2
XTAL1
AD0/D0
AD1/D1
AD2/D2
AD3/D3
AD4/D4
AD5/D5
AD6/D6
AD7/D7
DS80C390 Dual CAN High-Speed Microprocessor
FUNCTION
+5V
Digital Circuit Ground
Address Latch Enable, Output. When the MUX pin is low, this pin
outputs a clock to latch the external address LSB from the
multiplexed address/data bus on Port 0. This signal is commonly
connected to the latch enable of an external transparent latch. ALE
has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1
cycles. When the MUX pin is high, the pin will toggle continuously if
the ALEOFF bit is cleared. ALE is forced high when the device is in a
reset condition or if the ALEOFF bit is set while the MUX pin is high.
Program Store Enable, Output. This signal is the chip enable for
external ROM memory. PSEN provides an active-low pulse and is
driven high when external ROM is not being accessed.
External Access Enable, Input. This pin must be wired to GND for
proper operation.
Multiplex/Demultiplex Select, Input. This pin selects if the
address/data bus operates in multiplexed (MUX = 0) or demultiplexed
(MUX = 1) mode.
Reset, Input. The RST input pin contains a Schmitt voltage input to
recognize external active-high reset inputs. The pin also employs an
internal pulldown resistor to allow for a combination of wired-OR
external reset sources. An RC circuit is not required for power-up, as
the device provides this function internally.
Reset Output Low, Output. This active-low signal is asserted:
When the processor has entered reset through the RST pin,
During crystal warmup period following power-on or stop mode,
During a watchdog timer reset (2 cycles duration),
During an oscillator failure (if OFDE = 1),
Whenever V_CC ≤ V_RST.
XTAL1, XTAL2. Crystal oscillator pins support fundamental mode,
parallel resonant, and AT-cut crystals. XTAL1 is the input if an
external clock source is used in place of a crystal. XTAL2 is the
output of the crystal amplifier.
AD0–7 (Port 0), I/O. When the MUX pin is wired low, Port 0 is the
multiplexed address/data bus. While ALE is high, the LSB of a
memory address is presented. While ALE falls, the port transitions to
a bidirectional data bus. When the MUX pin is wired high, Port 0
functions as the bidirectional data bus. Port 0 cannot be modified by
software. The reset condition of Port 0 pins is high. No pullup
resistors are needed.
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