DS80C390_05 Datasheet, PDF (37/53 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

DS80C390 Dual CAN High-Speed Microprocessor
Table 9. Data Memory Cycle Stretch Values
MD2 MD1 MD0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
STRETCH
CYCLE
COUNT
0*
1**
2
3
4
5
6
7
MOVX
MACHINE
CYCLES
2
3
4
5
9
10
11
12
RD, WR PULSE WIDTH (IN OSCILLATOR CLOCKS)
t_MCS
(4X/2X = 1
CD1:0 = 00)
0.5 t_CLCL
t_CLCL
2 t_CLCL
3 t_CLCL
4 t_CLCL
5 t_CLCL
6 t_CLCL
7 t_CLCL
t_MCS
(4X/2X = 0
CD1:0 = 00)
1 t_CLCL
2 t_CLCL
4 t_CLCL
6 t_CLCL
8 t_CLCL
10 t_CLCL
12 t_CLCL
14 t_CLCL
t_MCS
(4X/2X = X
CD1:0 = 10)
2 t_CLCL
4 t_CLCL
8 t_CLCL
12 t_CLCL
16 t_CLCL
20 t_CLCL
24 t_CLCL
28 t_CLCL
t_MCS
(4X/2X = X
CD1:0 = 11)
2048 t_CLCL
4096 t_CLCL
8192 t_CLCL
12,288 t_CLCL
16,384 t_CLCL
20,480 t_CLCL
24,576 t_CLCL
28,672 t_CLCL
*All internal MOVX operations execute at the 0 Stretch setting.
**Default stretch setting for external MOVX operations following reset.
EXTENDED STACK POINTER
The DS80C390 supports both the traditional 8-bit and an extended 10-bit stack pointer that improves the
performance of large programs written in high-level languages such as C. Enable the 10-bit stack pointer feature by
setting the stack address mode bit, SA (ACON.2). The bit is cleared following a reset, forcing the device to use an
8-bit stack located in the scratchpad RAM area. When the SA bit is set, the device will address up to 1kB of stack
memory in the first 1kB of the internal MOVX memory. The 10-bit stack pointer address is generated by
concatenating the lower two bits of the extended stack pointer (ESP;9Bh) and the traditional 8051 stack pointer
(SP;81h). The 10-bit stack pointer cannot be enabled when the 4kB of SRAM is mapped as both program and data
memory.
ENHANCED DUAL DATA POINTERS
The DS80C390 contains two data pointers, DPTR0 and DPTR1, designed to improve performance in applications
that require high data throughput. Incorporating a second data pointer allows the software to greatly speed up block
data (MOVX) moves by using one data pointer as a source register and the other as the destination register.
DPTR0 is located at the same address as the original 8051 data pointer, allowing the DS80C390 to execute
standard 8051 code with no modifications. The second data pointer, DPTR1, is split between the DPH1 and DPL1
SFRs, similar to the DPTR0 configuration. The active data pointer is selected with the data pointer select bit SEL
(DPS.0). Any instructions that reference the DPTR (i.e., MOVX A, @DPTR), will select DPTR0 if SEL = 0, and
DPTR1 if SEL = 1. Because the bits adjacent to SEL are not implemented, the state of SEL (and thus the active
data pointer) can be quickly toggled by the INC DPS instruction without disturbing other bits in the DPS register.
Unlike the standard 8051, the DS80C390 has the ability to decrement as well as increment the data pointers
without additional instructions. When the INC DPTR instruction is executed, the active DPTR increments or
decrements according to the ID1, ID0 (DPS.7-6), and SEL (DPS.0) bits as shown. The inactive DPTR is not
affected.
Table 10. Data Pointer Auto Increment/
Decrement Configuration
ID1 ID0 SEL
X
0
0
X
1
0
0
X
1
1
X
1
INC DPTR RESULT
Increment DPTR0
Decrement DPTR0
Increment DPTR1
Decrement DPTR1
Another useful feature of the device is its ability to automatically switch the active data pointer after a DPTR-based
instruction is executed. This feature can greatly reduce the software overhead associated with data memory block
moves, which toggle between the source and destination registers. When the toggle-select bit (TSL;DPS.5) is set
to 1, the SEL bit (DPS.0) is automatically toggled every time one of the following DPTR-related instructions is
executed.
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