DS80C390_05 Datasheet, PDF (43/53 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

DS80C390 Dual CAN High-Speed Microprocessor
The SCON0 register provides control for serial port 0 while its I/O buffer is SBUF0. The registers SCON1 and
SBUF1 provide the same functions for the second serial port. A full description of the use and operation of both
serial ports can be found in the High-Speed Microcontroller User’s Guide: DS80C390 Supplement.
WATCHDOG TIMER
The watchdog is a free-running, programmable timer that can set a flag, cause an interrupt, and/or reset the
microcontroller if allowed to reach a preselected timeout. It can be restarted by software.
A typical application uses the watchdog timer as a reset source to prevent software from losing control. The
watchdog timer is initialized, selecting the timeout period and enabling the reset and/or interrupt functions. After
enabling the reset function, software must then restart the timer before its expiration or the hardware will reset the
CPU. In this way, if the code execution goes awry and software does not reset the watchdog as scheduled, the
processor is put in a known good state: reset.
Software can select one of four timeout values as controlled by the WD1 and WD0 bits. Timeout values are precise
since they are a function of the crystal frequency. When the watchdog times out, it sets the watchdog timer-reset
flag (WTRF = WDCON.2), which generates a reset if enabled by the enable watchdog-timer reset (EWT =
WDCON.1) bit. Both the enable watchdog-timer reset and the reset watchdog timer control bits are protected by
timed-access circuitry. This prevents errant software from accidentally clearing or disabling the watchdog.
The watchdog interrupt is useful for systems that do not require a reset circuit. It set the WDIF (watchdog interrupt)
flag 512 clocks before setting the reset flag. Software can optionally enable this interrupt source, which is
independent of the watchdog-reset function. The interrupt is commonly used during the debug process to
determine where watchdog-reset commands must be located in the application software. The interrupt also can
serve as a convenient time base generator or can wake up the processor from power-saving modes.
The clock control (CKCON) and the watchdog control (WDCON) SFRs control the watchdog timer. CKCON.7 and
CKCON.6 (WD1 and WD0, respectively) select the watchdog timeout period. Of course, the 4X/2X (PMR.3) and
CD1:0 (PMR.7:6) system clock-control bits also affect the timeout period. Table 12 shows the timeout selection.
Table 12. Watchdog Timeout Values
4X/2X
1
0
x
x
x
CD1:0
00
00
01
10
11
WATCHDOG INTERRUPT TIMEOUT
WATCHDOG RESET TIMEOUT
WD1:0 = 00 WD1:0 = 01 WD1:0 = 10 WD1:0 = 11 WD1:0 = 00 WD1:0 = 01
2¹⁵
2¹⁸
2²¹
2²⁴
2¹⁵+512
2¹⁸+512
2¹⁶
2¹⁹
2²²
2²⁵
2¹⁶+512
2¹⁹+512
2¹⁷
2²⁰
2²³
2²⁶
2¹⁷+512
2²⁰+512
2¹⁷
2²⁰
2²³
2²⁶
2¹⁷+512
2²⁰+512
2²⁵
2²⁸
2³¹
2³⁴
2²⁵+512
2²⁸+512
WD1:0 = 10
2²¹+512
2²²+512
2²³+512
2²³+512
2³¹+512
WD1:0 = 11
2²⁴+512
2²⁵+512
2²⁶+512
2²⁶+512
2³⁴+512
Table 12 demonstrates that for a 33MHz crystal frequency, the watchdog timer can produce timeout periods from
3.97ms (2¹⁷ x 1/33MHz) to over 2 seconds (2.034 = 2²⁶ x 1/33MHz) with the default setting of CD1:0 (=10). This
wide variation in timeout periods allows very flexible system implementation.
In a typical initialization, the user selects one of the possible counter values to determine the timeout. Once the
counter chain has completed a full count, hardware sets the interrupt flag (WDIF = WDCON.3). Regardless of
whether the software makes use of this flag, there are then 512 clocks left until the reset flag (WTRF = WDCON.2)
is set. Software can enable (1) or disable (0) the reset using the enable watchdog-timer-reset (EWT = WDCON.1)
bit.
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