DS80C390_05 Datasheet, PDF (38/53 Pages) Dallas Semiconductor – Dual CAN High-Speed Microprocessor

DS80C390 Dual CAN High-Speed Microprocessor
INC DPTR
MOV DPTR, #data16
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
As a brief example, if TSL is set to 1, then both data pointers can be updated with two INC DPTR instructions.
Assume that SEL = 0, making DPTR the active data pointer. The first INC DPTR increments DPTR and toggles
SEL to 1. The second instruction increments DPTR1 and toggles SEL back to 0.
INC DPTR
INC DPTR
CLOCK CONTROL AND POWER MANAGEMENT
The DS80C390 includes a number of unique features that allow flexibility in selecting system clock sources and
operating frequencies. To support the use of inexpensive crystals while allowing full speed operation, a clock
multiplier is included in the processor’s clock circuit. Also, in addition to the standard 80C32 idle and power-down
(Stop) modes, the DS80C390 provides a new power management mode. This mode allows the processor to
continue instruction execution, yet at a very low speed to significantly reduce power consumption (below even idle
mode). The DS80C390 also features several enhancements to stop mode that make this extremely low-power
mode more useful. Each of these features is discussed in detail below.
System Clock Control
As mentioned previously, the microcontroller contains special clock-control circuitry that simultaneously provides
maximum timing flexibility and maximum availability and economy in crystal selection. The logical operation of the
system clock-divide control function is shown in Figure 29. A 3:1 multiplexer, controlled by CD1, CD0 (PMR.7-6),
selects one of three sources for the internal system clock:
Crystal oscillator or external clock source
(Crystal oscillator or external clock source) divided by 256
(Crystal oscillator or external clock source) frequency multiplied by 2 or 4 times
Figure 29. System Clock Control Diagram
The system clock-control circuitry generates two clock signals that are used by the microcontroller. The internal
system clock provides the time base for timers and internal peripherals. The system clock is run through a divide-
by-4 circuit to generate the machine cycle clock that provides the time base for CPU operations. All instructions
execute in one to five machine cycles. It is important to note the distinction between these two clock signals, as
they are sometimes confused, creating errors in timing calculations.
Setting CD1, CD0 to 0 enables the frequency multiplier, either doubling or quadrupling the frequency of the crystal
oscillator or external clock source. The 4X/2X bit controls the multiplying factor, selecting twice or four times the
frequency when set to 0 or 1, respectively. Enabling the frequency multiplier results in apparent instruction
execution speeds of 2 or 1 clocks. Regardless of the configuration of the frequency multiplier, the system clock of
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