PSOC4200M Datasheet, PDF (9/42 Pages) Cypress Semiconductor – Programmable System-on-Chip

PSoC^® 4: PSoC 4200M Family
Datasheet
GPIO
The PSoC 4200M has 55 GPIOs in the 68-pin QFN package.
The GPIO block implements the following:
■ Eight drive strength modes including strong push-pull, resistive
pull-up and pull-down, weak (resistive) pull-up and pull-down,
open drain and open source, input only, and disabled
■ Input threshold select (CMOS or LVTTL)
■ Individual control of input and output disables
■ Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode and Hibernate modes)
■ Selectable slew rates for dV/dt related noise control to improve
EMI
The pins are organized in logical entities called ports, which are
8-bit in width. During power-on and reset, the blocks are forced
to the disable state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a
high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin. Pin locations for
fixed-function peripherals are also fixed to reduce internal multi-
plexing complexity (these signals do not go through the DSI
network). DSI signals are not affected by this and any pin on
Ports 0, 1, 2, and 3 may be routed to any UDB through the DSI
network. Only pins on Ports 0, 1, 2, and 3 may be routed through
DSI signals.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (8 for PSoC 4200M).
The Pins of Port 6 (up to 6 depending on the package) are
overvoltage tolerant (V_IN can exceed V_DD). The overvoltage cells
will not sink
compliance
more than 10 µA when
with I²C specifications.
their
inputs
exceed
V_DDIO
in
Special Function Peripherals
LCD Segment Drive
The PSoC 4200M has an LCD controller, which can drive up to
four commons and up to 51 segments. Any pin can be either a
common or a segment pin. It uses full digital methods to drive the
LCD segments requiring no generation of internal LCD voltages.
The two methods used are referred to as digital correlation and
PWM.
Digital correlation pertains to modulating the frequency and
levels of the common and segment signals to generate the
highest RMS voltage across a segment to light it up or to keep
the RMS signal zero. This method is good for STN displays but
may result in reduced contrast with TN (cheaper) displays.
PWM pertains to driving the panel with PWM signals to effec-
tively use the capacitance of the panel to provide the integration
of the modulated pulse-width to generate the desired LCD
voltage. This method results in higher power consumption but
can result in better results when driving TN displays. LCD
operation is supported during Deep Sleep refreshing a small
display buffer (4 bits; 1 32-bit register per port).
CapSense
CapSense is supported on all pins in the PSoC 4200M through
a CapSense Sigma-Delta (CSD) block that can be connected to
any pin through an analog mux bus that any GPIO pin can be
connected to via an Analog switch. CapSense functionality can
thus be provided on any pin or group of pins in a system under
software control. A component is provided for the CapSense
block, which provides automatic hardware tuning (Cypress
SmartSense™), to make it easy for the user.
Shield voltage can be driven on another Mux Bus to provide
water tolerance capability. Water tolerance is provided by driving
the shield electrode in phase with the sense electrode to keep
the shield capacitance from attenuating the sensed input.
Each CSD block has two IDACs which can be used for general
purposes if CapSense is not being used.(both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available). The PSoC 4200M has two
CSD blocks which can be used independently; one for
CapSense and one providing two IDACs.
The two CapSense blocks are referred to as CSD0 and CSD1.
Capacitance sensing inputs on Ports 0, 1, 2, 3, 4, 6, and 7 are
sensed by CSD0. Capacitance sensing inputs on Port 5 are
sensed by CSD1.
Document Number: 001-93963 Rev. *G
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