PSOC4200M Datasheet, PDF (6/42 Pages) Cypress Semiconductor – Programmable System-on-Chip

PSoC^® 4: PSoC 4200M Family
Datasheet
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the low-frequency clock; this allows watchdog operation during
Deep Sleep and generates a watchdog reset or an interrupt if not
serviced before the timeout occurs. The watchdog reset is
recorded in the Reset Cause register.
Reset
The PSoC 4200M can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the reset. An XRES pin is
reserved for external reset to avoid complications with configu-
ration and multiple pin functions during power-on or reconfigu-
ration.
Voltage Reference
The PSoC 4200M reference system generates all internally
required references. A 1% voltage reference spec is provided for
the 12-bit ADC. To allow better signal-to-noise ratios (SNR) and
better absolute accuracy, it is possible to add an external bypass
capacitor to the internal reference using a GPIO pin or to use an
external reference for the SAR.
Analog Blocks
12-bit SAR ADC
The 12-bit 1 MSample/second SAR ADC can operate at a
maximum clock rate of 18 MHz and requires a minimum of 18
clocks at that frequency to do a 12-bit conversion.
The block functionality is augmented for the user by adding a
reference buffer to it (trimmable to ±1%) and by providing the
choice of three internal voltage references: V_DD, V_DD/2, and
V_REF (nominally 1.024 V) as well as an external reference
through a GPIO pin. The Sample-and-Hold (S/H) aperture is
programmable allowing the gain bandwidth requirements of the
amplifier driving the SAR inputs, which determine its settling
time, to be relaxed if required. The system performance will be
65 dB for true 12-bit precision if appropriate references are used
and system noise levels permit. To improve performance in noisy
conditions, it is possible to provide an external bypass (through
a fixed pin location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer (expandable to 16 inputs). The sequencer cycles
through selected channels autonomously (sequencer scan) and
does so with zero switching overhead (that is, the aggregate
sampling bandwidth is equal to 1 Msps, whether it is for a single
channel or distributed over several channels). The sequencer
switching is effected through a state machine or through
firmware-driven switching. A feature provided by the sequencer
is buffering of each channel to reduce CPU interrupt service
requirements. To accommodate signals with varying source
impedance and frequency, it is possible to have different sample
times programmable for each channel. In addition, the signal
range specification through a pair of range registers (low and
high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
The SAR is able to digitize the output of the on-board temper-
ature sensor for calibration and other temperature-dependent
functions. The SAR is not available in Deep Sleep and Hibernate
modes as it requires a high-speed clock (up to 18 MHz). The
SAR operating range is 1.71 to 5.5 V.
Figure 3. SAR ADC System Diagram
Sequencing
and Control
AHB System Bus and Programmable Logic
Interconnect
SARSEQ
POS
SARADC
NEG
Data and
Status Flags
Inputs from other Ports
Reference
Selection
VDD/2 VDDD VREF
External
Reference
and
Bypass
(optional)
Document Number: 001-93963 Rev. *G
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