PSOC4200M Datasheet, PDF (7/42 Pages) Cypress Semiconductor – Programmable System-on-Chip

PSoC^® 4: PSoC 4200M Family
Datasheet
Analog Multiplex Bus
The PSoC 4200M has two concentric analog buses (Analog Mux
Bus A and Analog Mux Bus B) that circumnavigate the periphery
of the chip. These buses can transport analog signals from any
pin to various analog blocks (including the opamps) and to the
CapSense blocks allowing, for instance, the ADC to monitor any
pin on the chip. These buses are independent and can also be
split into three independent sections. This allows one section to
be used for CapSense purposes, one for general analog signal
processing, and the third for general-purpose digital peripherals
and GPIO.
Four Opamps
The PSoC 4200M has four opamps with comparator modes,
which allow most common analog functions to be performed
on-chip eliminating external components; PGAs, voltage buffers,
filters, trans-impedance amplifiers, and other functions can be
realized with external passives saving power, cost, and space.
The on-chip opamps are designed with enough bandwidth to
drive the Sample-and-Hold circuit of the ADC without requiring
external buffering. The opamps can operate in the Deep Sleep
mode at very low power levels. The following diagram shows one
of two identical opamp pairs of the opamp subsystem.
Figure 4. Identical Opamp Pairs in Opamp Subsystem
OA0 _10x
+
P0
-
1x
Internal
Out0
P1
P2
P3
P4
OA1 _1x
P5
-
P6
+
10x
Internal
Out1
P7
The ovals in Figure 4 represent analog switches, which may be
controlled via user firmware, the SAR sequencer, or user-defined
programmable logic. The opamps (OA0 and OA1) are configu-
rable via these switches to perform all standard opamp functions
with appropriate feedback components.
The opamps (OA0 and OA1) are programmable and reconfigu-
rable to provide standard opamp functionality via switchable
feedback components, unity gain functionality for driving pins
directly, or for internal use (such as buffering SAR ADC inputs as
indicated in the diagram), or as true comparators.
The opamp inputs provide highly flexible connectivity and can
connect directly to dedicated pins or, via the analog mux buses,
Document Number: 001-93963 Rev. *G
to any pin on the chip. Analog switch connectivity is controllable
by user firmware as well as user-defined programmable digital
state machines (implemented via UDBs).
The opamps operate in Deep Sleep mode at very low currents
allowing analog circuits to remain operational during Deep
Sleep.
Temperature Sensor
The PSoC 4200M has one on-chip temperature sensor. This
consists of a diode, which is biased by a current source that can
be disabled to save power. The temperature sensor is connected
to the ADC, which digitizes the reading and produces a temper-
ature value using Cypress-supplied software that includes
calibration and linearization.
Low-power Comparators
The PSoC 4200M has a pair of low-power comparators, which
can also operate in the Deep Sleep and Hibernate modes. This
allows the analog system blocks to be disabled while retaining
the ability to monitor external voltage levels during low-power
modes. The comparator outputs are normally synchronized to
avoid meta-stability unless operating in an asynchronous power
mode (Hibernate) where the system wake-up circuit is activated
by a comparator switch event.
Programmable Digital
Universal Digital Blocks (UDBs) and Port Interfaces
The PSoC 4200M has four UDBs; the UDB array also provides
a switched Digital System Interconnect (DSI) fabric that allows
signals from peripherals and ports to be routed to and through
the UDBs for communication and control. The UDB array is
shown in the following figure.
Figure 5. UDB Array
AHB Bridge CPUSS Dig CLKS
8 to 32
4 to 8
UDBIF
BUS IF IRQ IF CLK IF
PoPrPtooIrFrtt _IIFF
Routing
Channels
DSI
UDB
DSI
UDB
Scalable array of
UDBs (max=16)
UDB
UDB
DSI
DSI
Programmable Digital Subsystem
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