CY8CTMG200-32LQXI Datasheet, PDF (85/309 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

11. TrueTouch Module
This chapter presents the TrueTouch Module and its associated registers. For a quick reference of all PSoC registers in
address order, refer to the Register Reference chapter on page 187.
11.1 Architectural Description
11.1.1 Types of TrueTouch Approaches
A block diagram of the overall capacitive sensing architec-
ture is shown in Figure 11-1. CS1 through CSN are the
capacitors being measured. The various sensing
approaches use different subsets of this hardware.
Figure 11-1. TrueTouch Module Block Diagram
IDAC
CS1
CS2
Vr
Reference
Buffer
Comparator
+ ^Mux
- _Mux
Refs
TrueTouch Counters
CSCLK
IMO
TrueTouch
Clock Select
Relaxation
Oscillator (RO)
CSN
C_INTERNAL
C_EXTERNAL
11.1.1.1 Positive Charge Integration
In the positive charge integration method, charge on a
sense capacitor is integrated onto a larger capacitor, starting
from ground. The number of cycles required to reach a tar-
get voltage gives a measurement of the sensed capaci-
tance. The hardware configuration for this approach is
shown in Figure 11-2. The hardware supports the use of
either pin P0[1] or P0[3] for the external integration capaci-
tor.
Figure 11-2. Positive Charge Integration Block Diagram
Pin Enables
Reference ^CSCLK
Buffer
Vr
CSCLK
Comparator
Mux
Mux
Refs
TrueTouch Logic
16-Bit Counter
CSCLK
s
CS1
CS2
CSN
C_EXTERNAL
P0[1] or
P0[3]
IMO
TrueTouch
Clock Select
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
85
[+] Feedback