CY8CTMG200-32LQXI Datasheet, PDF (34/309 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

Supervisory ROM (SROM)
The following code example puts the correct value in KEY1
and KEY2. The code is preceded by a HALT, to force the
program to jump directly into the setup code and not acci-
dentally run into it.
1.
halt
2.
SSCOP: mov [KEY1], 3ah
3.
mov X, SP
4.
mov A, X
5.
add A, 3
6.
mov [KEY2], A
3.1.1 Additional SROM Feature
Return Codes: These aid in the determination of success
or failure of a particular function. The return code is stored in
KEY1’s position in the parameter block. The Checksum and
TableRead functions do not have return codes because
KEY1’s position in the parameter block is used to return
other data.
Table 3-3. SROM Return Code Meanings
Return Code
Value
00h
01h
02h
03h
04h
06h
Description
Success.
Function not allowed because of block level protection.
Software reset without hardware reset.
Fatal error, SROM halted.
Write and Verify error.
Failure of Smartwrite parameters CheckSum
Note Read, write, and erase operations may fail if the target
block is read or write protected. Block protection levels are
set during device programming and cannot be modified from
code in the PSoC device.
3.1.2 SROM Function Descriptions
3.1.2.1 SWBootReset Function
The SROM function SWBootReset is responsible for transi-
tioning the device from a reset state to running user code.
See Chapter “System Resets” on page 135 for more infor-
mation on what events causes the SWBootReset function to
execute.
The SWBootReset function executes whenever the SROM
is entered with an M8C accumulator value of 00h; the SRAM
parameter block is not used as an input to the function. This
happens, by design, after a hardware reset because the
M8C's accumulator is reset to 00h or when user code exe-
cutes the SSC instruction with an accumulator value of 00h.
If the checksum of the calibration data is valid, the
SWBootReset function ends by setting the internal M8C reg-
isters (CPU_SP, CPU_PC, CPU_X, CPU_F, CPU_A) to 00h,
writing 00h to most SRAM addresses in SRAM Page 0, and
then begins to execute user code at address 0000h. (See
Table 3-5 and the following paragraphs for more information
on which SRAM addresses are modified.) If the checksum is
not valid, an internal reset is executed and the boot process
starts over. If this condition occurs, the internal reset status
bit (IRESS) is set in the CPU_SCR1 register.
In devices with more than 256 bytes of SRAM, no SRAM is
modified by the SWBootReset function in SRAM pages
numbered higher than '0'.
Table 3-5 documents the value of all the SRAM addresses in
Page 0 after a successful SWBootReset. A value of "xx"
indicates that the SRAM address is not modified by the
SWBootReset function. A hex value indicates that the
address always has the indicated value after a successful
SWBootReset. A "??" indicates that the value, after a
SWBootReset, is determined by the value of the IRAMDIS
bit in the CPU_SCR1 register. If IRAMDIS is not set, these
addresses are initialized to 00h. If IRAMDIS is set, these
addresses are not modified by a SWBootReset after a
watchdog reset.
34
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
[+] Feedback