CY8CTMG200-32LQXI Datasheet, PDF (25/309 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

Section B: PSoC Core
Summary Table of the Core Registers (continued)
Address
Name
1,DCh
IO_CFG1
Bit 7
StrongP
Bit 6
Bit 5
Bit 4
Range[1:0]
Bit 3
P1_LOW_
THRS
Bit 2
SPICLK_ON
_P10
Bit 1
REG_EN
Bit 0
IOINT
Access
RW : 00
INTERNAL MAIN OSCILLATOR (IMO) REGISTER (page 64)
1,E8h
1,FAh
x,FEh
1,E2h
IMO_TR
IMO_TR1
CPU_SCR1
OSC_CR2
IRESS
Trim[7:0]
SLIM[1:O]
CLK48MEN
Fine Trim[2:0]
EXTCLKEN
IMODIS
IRAMDIS
W: 00
RW : 00
# : 00
RW : 00
INTERNAL LOW SPEED OSCILLATOR (ILO) REGISTER (page 68)
1,E9h
ILO_TR
PD_MODE ILOFREQ SATBIASB
Freq Trim[3:0]
RW : 18
EXTERNAL CRYSTAL OSCILLATOR (ECO) REGISTERS (page 69)
1,D2h
1,D3h
1,E1h
ECO_ENBUS
ECO_TRIM
ECO_CFG
ECO_ENBUS[2:0]
ECO_XGM[2:0]
ECO_PL[1:0]
ECO_LPM ECO_EXW ECO_EX
RW : 07
RW : 00
RW : 00
SLEEP AND WATCHDOG REGISTERS (page 77)
0,E3h
1,EBh
1,ECh
1,EDh
RES_WDT
SLP_CFG
SLP_CFG2
SLP_CFG3
PSSDC[1:0]
DBL_TAPS
WDSL_Clear[7:0]
T2TAP [1:0]
ALT_Buzz [1:0]
T1TAP [1:0]
I2C_ON
LSO_OFF
T0TAP [1:0]
W : 00
RW : 0
RW : 00
RW : 0x7F
LEGEND
L The and f, expr; or f, expr; and xor f, expr instructions can be used to modify this register.
x An “x” before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used.
C Clearable register or bit(s).
R Read register or bit(s).
W Write register or bit(s).
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
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