CY8CTMG200-32LQXI Datasheet, PDF (121/309 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

I2C Slave
The following diagram illustrates an example of how the address pointers are configured in EZI2C mode. In this example, the
external master sent a Start, Slave Address, and a data byte of 2 to initialize both the base address pointer (I2C_BP register)
and the current address pointer (I2C_CP register). Then, 4 bytes were written, OR a Start or Restart was sent with the device
address, and 4 bytes were read. On the CPU side, a 2 was written to the CPU base address register (CPU_BP register), and
6 subsequent bytes were read from or written to the I2C_BUFF register by the CPU.
Figure 15-5. Address Pointer in EZI2C Mode
Transmit Data
Bytes to I2C
Interface
Receive Data
Bytes from I2C
Interface
I2C Base Pointer
(I2C_BP)
2
I2C Current Pointer
(I2C_CP)
6
Buffer Module
0
1
2
3
4
5
6
7
8
9
32-Byte
RAM
CPU Base Pointer
(CPU_BP)
2
CPU Current Pointer
(CPU_CP)
8
Transmit Data
Bytes from CPU
(CPU Write to
I2C_BUFF)
Receive Data
Bytes to CPU
(CPU Read from
I2C_BUFF)
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
121
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