CY8CTMG200-32LQXI Datasheet, PDF (184/309 Pages) Cypress Semiconductor – Technical Reference Manual (TRM)

Section E: Registers
Register Map Bank 0 Table: User Space
PRT0DR
00 RW 188 EP1_CNT0
PRT0IE
01 RW 189 EP1_CNT1
02
EP2_CNT0
03
EP2_CNT1
PRT1DR
04 RW 188 EP3_CNT0
PRT1IE
05 RW 189 EP3_CNT1
06
EP4_CNT0
07
EP4_CNT1
PRT2DR
08 RW 188 EP5_CNT0
PRT2IE
09 RW 189 EP5_CNT1
0A
EP6_CNT0
0B
EP6_CNT1
PRT3DR
0C RW 188 EP7_CNT0
PRT3IE
0D RW 189 EP7_CNT1
0E
EP8_CNT0
0F
EP8_CNT1
PRT4DR
10 RW 188
PRT4IE
11 RW 189
12
13
14
15
16
17
18
PMA0_DR
19
PMA1_DR
1A
PMA2_DR
1B
PMA_DR
1C
PMA4_DR
1D
PMA5_DR
1E
PMA6_DR
1F
PMA7_DR
20
21
AMUX_CFG
22
23
24
PMA8_DR
25
PMA9_DR
26
PMA10_DR
27
PMA11_DR
28
PMA12_DR
SPI_TXR
29 W 190 PMA13_DR
SPI_RXR
2A R 191 PMA14_DR
SPI_CR
2B
# 192 PMA15_DR
2C
TMP_DR0
2D
TMP_DR1
2E
TMP_DR2
2F
TMP_DR3
30
USB_SOF0
31
R 193
USB_SOF1
32
R 194
USB_CR0
33 RW 195
USBIO_CR0 34
# 196
USBIO_CR1 35
EP0_CR
36
EP0_CNT0
37
# 197
# 198
# 199
EP0_DR0
38 RW 200 CMP_RDC
EP0_DR1
39 RW 200 CMP_MUX
EP0_DR2
3A RW 200 CMP_CR0
EP0_DR3
3B RW 200 CMP_CR1
EP0_DR4
3C RW 200 CMP_LUT
EP0_DR5
3D RW 200
EP0_DR6
EP0_DR7
3E RW 200
3F RW 200
Gray fields are reserved. # Access is bit specific.
40
# 201
41 RW 202
42
# 201
43 RW 202
44
# 201
45 RW 202
46
# 201
47 RW 202
48
# 201
49 RW 202
4A
# 201
4B RW 202
4C
#
201
4D RW 202
4E
# 201
4F RW 202
50
51
52
53
54
55
56
57
58 RW 203
59 RW 203
5A RW 203
5B RW 203
5C RW 203
5D RW 203
5E RW 203
5F RW 203
60
CS_CR0
61 RW 204 CS_CR1
62
CS_CR2
63
CS_CR3
64 RW 203 CS_CNTL
65 RW 203 CS_CNTH
66 RW 203 CS_STAT
67 RW 203 CS_TIMER
68 RW 203 CS_SLEW
69 RW 203 PRS_CR
6A RW 203
6B RW 203
6C RW 266
6D RW 266
6E RW 266
6F RW 266
70
PT0_CFG
71
PT0_DATA1
72
PT0_DATA0
73
PT1_CFG
74
PT1_DATA1
75
PT1_DATA0
76
PT2_CFG
77
PT2_DATA1
78
# 205 PT2_DATA0
79 RW 206
7A RW 207
7B RW 208
7C RW 210
7D
7E
7F
80
C0
81
C1
82
C2
83
C3
84
C4
85
C5
86
C6
87
C7
88
I2C_XCFG
C8 RW 226
89
I2C_XSTAT C9
R 227
8A
I2C_ADDR
CA RW 228
8B
I2C_BP
CB
R
229
8C
I2C_CP
CC
R
230
8D
CPU_BP
CD RW 231
8E
CPU_CP
CE
R
232
8F
I2C_BUF
CF RW 233
90
CUR_PP
D0 RW 234
91
STK_PP
D1 RW 235
92
D2
93
IDX_PP
D3 RW 236
94
MVR_PP
D4 RW 237
95
MVW_PP
D5 RW 238
96
I2C_CFG
D6 RW 239
97
I2C_SCR
D7
#
240
98
I2C_DR
D8 RW 241
99
D9
9A
INT_CLR0
DA RW
242
9B
INT_CLR1
DB RW
244
9C
INT_CLR2
DC RW
246
9D
DD
9E
INT_MSK2
DE RW
248
9F
INT_MSK1
DF RW
249
A0 RW 211 INT_MSK0
E0 RW
250
A1 RW 212 INT_SW_EN E1 RW
251
A2 RW 213 INT_VC
E2 RC
252
A3 RW 214 RES_WDT
E3 W
253
A4 RW 215
E4
A5 RW 216
E5
A6
#
217
E6
A7 RW 218
E7
A8 RW 219
E8
A9 RW 220
E9
AA
EA
AB
EB
AC
EC
AD
ED
AE
EE
AF
EF
B0 RW 221
F0
B1 RW 223
F1
B2 RW 223
F2
B3 RW 224
F3
B4 RW 223
F4
B5 RW 223
F5
B6 RW 225
F6
B7 RW 223 CPU_F
F7 RL 254
B8 RW 223
F8
B9
F9
BA
FA
BB
FB
BC
FC
BD
IDAC_D
FD RW 256
BE
CPU_SCR1 FE
#
257
BF
CPU_SCR0 FF
#
258
184
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
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